1. Field of the Invention
The invention pertains to a circuit arrangement or a comparator according to the preamble of claim 1.
2. Description of the Prior the Art
A circuit arrangement of this type is, for example, described in G. M. Yin et al., “A High-Speed CMOS Comparator with 8-b Resolution,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, February, 1992, and serves for the discrete-time comparison of a first input signal with a second input signal (frequently a constant reference signal or a threshold), as well as for making available a pair of complementary binary output signals which corresponds to the result of the comparison (logic level).
A comparison of two input signals with one another respectively takes place in three successive time intervals that, according to this application, are referred to as reset, phase 1 and phase 2. In the above-mentioned IEEE article, the corresponding time intervals are referred to as “reset time interval,” “first step of regeneration” and “second step of regeneration.” With respect to the function and optimization of such a circuit arrangement, we hereby refer to the aforementioned IEEE Article, in which these aspects are described in detail.
In summation, a pair of complementary binary output signals which corresponds to the result of the comparison is made available on a line pair as described below: in the reset phase, the first flip-flop is changed over into an astable state. The difference between the input signals then leads to a comparatively small potential difference between the two lines in phase 1. This potential difference is then amplified with a certain time constant by the first flip-flop. In this case, it is decisive that the potential difference becomes as high as possible within the shortest possible time. A high-speed (small time constant) in this phase 1 is achieved if the capacitance of the first section of the line pair is as low as possible and the amplification (e.g., transconductance) of the first flip-flop simultaneously is as high as possible. It is usually not possible to simultaneously optimize these two parameters, i.e., an increase in the amplification of a flip-flop usually also leads to an increase in the capacitance (as well as the current consumption) in practical applications. Consequently, it is practical to find a suitable compromise between current consumption, capacitance and amplification for the respective application. In phase 2, the connecting circuit connects a second section of the line pair and consequently a second bistable flip-flop to the first section of the line pair such that the potential difference on the two lines is additionally amplified by the second flip-flop in phase 2. In this phase, it is attempted to bring both potentials to at least approximately logic levels, i.e., the desired complementary binary output potentials. In this case, the first flip-flop “draws” one of the two potentials to the first supply potential, with the second flip-flop drawing the other potential to the second supply potential. The problem can be seen in the fact that the amplification of the first flip-flop and consequently the speed in phase 2 is limited in practical applications due to the above-mentioned compromise with respect to the dimensions of the first flip-flop.
The function of such circuit arrangements that are also referred to as comparators below is required in various applications. One noteworthy example is the utilization of comparators in analog/digital converters. The main function of a comparator consists of making available the output signal(s) correctly and as rapidly as possible. In integrated circuit arrangements that, in particular, are designed for a high data throughput, comparators frequently represent a limiting component for the entire system due to their finite comparison speed.